Copper Plating for Advanced Semiconductor Packaging
As the semiconductor industry moves to more advanced packaging structures, the use of copper plating has continued to grow. Along with this growth, the requirements on the copper plating solutions and deposit have become more demanding. Technic’s Elevate® Copper products are formulated to meet these demanding requirements such as high-speed plating, excellent coplanarity, and very low deposit roughness.
From very tight RDL (redistribution layer) patterns with 2 micron spaces, to 200 micron tall copper pillars, the Elevate® Copper processes can be adjusted to offer optimum results on a variety of semiconductor packaging platforms including FOWLP (Fan Out Wafer Level Packaging), Fan-In WLP (Fan-In Wafer Level Packaging), Flip Chip and 2.5D/3D.
All Elevate® Copper processes can be monitored with our industry leading Technic Elevate® Analyzer. In addition, we offer unparalleled customer service that has made Technic a respected resource for quality around the globe.
Elevate® Cu 6370
High-speed copper plating bath able to achieve very fast plating rates on a variety of semiconductor applications while maintaining good WIW and WID coplanarity. 4 microns/minute or more can be attained on bump on passivation, bump on pad, and other advanced packaging structures while maintaining a WIW of <10% and a WID of <5%. Standard pillars, mega pillars, and RDL structures can all be plated successfully with Elevate® Cu 6370.
Elevate® Cu 6340
A low-stress copper bath that can be used for any application that requires a low-stress deposit such as a glass substrate. Plates at 1 – 2 microns/minute with virtually no internal stress.